x86 PIC 8259 defines More...

Macros
#define	PIC1 0x20 /* IO base address for master PIC */

#define	PIC2 0xA0 /* IO base address for slave PIC */

#define	PIC1_COMMAND PIC1

#define	PIC1_DATA (PIC1+1)

#define	PIC2_COMMAND PIC2

#define	PIC2_DATA (PIC2+1)

#define	ICW1_ICW4 0x01 /* ICW4 (not) needed */

#define	ICW1_SINGLE 0x02 /* Single (cascade) mode */

#define	ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */

#define	ICW1_LEVEL 0x08 /* Level triggered (edge) mode */

#define	ICW1_INIT 0x10 /* Initialization - required! */

#define	ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */

#define	ICW4_AUTO 0x02 /* Auto (normal) EOI */

#define	ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */

#define	ICW4_BUF_MASTER 0x0C /* Buffered mode/master */

#define	ICW4_SFNM 0x10 /* Special fully nested (not) */

#define	PIC_EOI 0x20

Detailed Description

x86 PIC 8259 defines

Macro Definition Documentation

◆ ICW1_ICW4

#define ICW1_ICW4 0x01 /* ICW4 (not) needed */

◆ ICW1_INIT

#define ICW1_INIT 0x10 /* Initialization - required! */

◆ ICW1_INTERVAL4

#define ICW1_INTERVAL4 0x04 /* Call address interval 4 (8) */

◆ ICW1_LEVEL

#define ICW1_LEVEL 0x08 /* Level triggered (edge) mode */

◆ ICW1_SINGLE

#define ICW1_SINGLE 0x02 /* Single (cascade) mode */

◆ ICW4_8086

#define ICW4_8086 0x01 /* 8086/88 (MCS-80/85) mode */

◆ ICW4_AUTO

#define ICW4_AUTO 0x02 /* Auto (normal) EOI */

◆ ICW4_BUF_MASTER

#define ICW4_BUF_MASTER 0x0C /* Buffered mode/master */

◆ ICW4_BUF_SLAVE

#define ICW4_BUF_SLAVE 0x08 /* Buffered mode/slave */

◆ ICW4_SFNM

#define ICW4_SFNM 0x10 /* Special fully nested (not) */

◆ PIC1

#define PIC1 0x20 /* IO base address for master PIC */

◆ PIC1_COMMAND

#define PIC1_COMMAND PIC1

◆ PIC1_DATA

#define PIC1_DATA (PIC1+1)

◆ PIC2

#define PIC2 0xA0 /* IO base address for slave PIC */

◆ PIC2_COMMAND

#define PIC2_COMMAND PIC2

◆ PIC2_DATA

#define PIC2_DATA (PIC2+1)

◆ PIC_EOI

#define PIC_EOI 0x20

Macros