coproc.h File Reference

Go to the source code of this file.

Macros
#define	CPSR_NEGATIVE   (1<<31)
#define	CPSR_ZERO   (1<<30)
#define	CPSR_CARRY   (1<<29)
#define	CPSR_OVERFLOW   (1<<28)
#define	CPSR_UNDERFLOW   (1<<27)
#define	CPSR_JAZELLE   (1<<24)
#define	CPSR_E   (1<<9)
#define	CPSR_A   (1<<8)
#define	CPSR_IRQ   (1<<7)
#define	CPSR_FIQ   (1<<6)
#define	CPSR_THUMB   (1<<5)
#define	ARM_MODE_USER   (0x10)
#define	ARM_MODE_FIQ   (0x11)
#define	ARM_MODE_IRQ   (0x12)
#define	ARM_MODE_SVC   (0x13)
#define	ARM_MODE_MON   (0x16)
#define	ARM_MODE_ABORT   (0x17)
#define	ARM_MODE_HYP   (0x1A)
#define	ARM_MODE_UNDEF   (0x1B)
#define	ARM_MODE_SYSTEM   (0x1F)
#define	SCTLR_MMU   (1)
#define	SCTLR_ALIGH   (1<<1)
#define	SCTLR_DCACHE   (1<<2)
#define	SCTLR_CP15BEN   (1<<5)
#define	SCTLR_ENDIAN   (1<<7)
#define	SCTLR_SWP   (1<<10)
#define	SCTLR_BRANCH_PRED   (1<<11)
#define	SCTLR_ICACHE   (1<<12)
#define	SCTLR_VECTOR   (1<<13)
#define	SCTLR_ROUNDROBIN   (1<<14)
#define	SCTLR_HWACCESS   (1<<17)
#define	SCTLR_WXN   (1<<19)
#define	SCTLR_UWXN   (1<<20)
#define	SCTLR_FASTINT   (1<<21)
#define	SCTLR_U   (1<<22)
#define	SCTLR_VE   (1<<24)
#define	SCTLR_EE   (1<<25)
#define	SCTLR_NMFI   (1<<27)
#define	SCTLR_TRE   (1<<28)
#define	SCTLR_AFE   (1<<29)
#define	SCTLR_THUMBEXC   (1<<30)
#define	ID_MIDR   p15, c0, 0, c0, 0
#define	ID_CTR   p15, c0, 0, c0, 1
#define	ID_TCMTR   p15, c0, 0, c0, 2
#define	ID_TLBTR   p15, c0, 0, c0, 3
#define	ID_MPIDR   p15, c0, 0, c0, 5
#define	ID_REVIDR   p15, c0, 0, c0, 6
#define	ID_PFR0   p15, c0, 0, c1, 0
#define	ID_PFR1   p15, c0, 0, c1, 1
#define	ID_DFR0   p15, c0, 0, c1, 2
#define	ID_AFR0   p15, c0, 0, c1, 3
#define	ID_MMFR0   p15, c0, 0, c1, 4
#define	ID_MMFR1   p15, c0, 0, c1, 5
#define	ID_MMFR2   p15, c0, 0, c1, 6
#define	ID_MMFR3   p15, c0, 0, c1, 7
#define	ID_ISAR0   p15, c0, 0, c2, 0
#define	ID_ISAR1   p15, c0, 0, c2, 1
#define	ID_ISAR2   p15, c0, 0, c2, 2
#define	ID_ISAR3   p15, c0, 0, c2, 3
#define	ID_ISAR4   p15, c0, 0, c2, 4
#define	ID_ISAR5   p15, c0, 0, c2, 5
#define	ID_CCSIDR   p15, c0, 1, c0, 0
#define	ID_CLIDR   p15, c0, 1, c0, 1
#define	ID_AIDR   p15, c0, 1, c0, 7
#define	ID_CCSELR   p15, c0, 2, c0, 0
#define	ID_VPIDR   p15, c0, 4, c0, 0
#define	ID_VMPIDR   p15, c0, 4, c0, 5
#define	ID_SCTLR   p15, c1, 0, c0, 0
#define	ID_ACTLR   p15, c1, 0, c0, 1
#define	ID_CPACR   p15, c1, 0, c0, 2
#define	ID_SCR   p15, c1, 0, c1, 0
#define	ID_SDER   p15, c1, 0, c1, 1
#define	ID_NSACR   p15, c1, 0, c1, 2
#define	ID_HSCTLR   p15, c1, 4, c0, 0
#define	ID_HACTLR   p15, c1, 4, c0, 1
#define	ID_HCR   p15, c1, 4, c1, 0
#define	ID_HDCR   p15, c1, 4, c1, 1
#define	ID_HCPTR   p15, c1, 4, c1, 2
#define	ID_HSTR   p15, c1, 4, c1, 3
#define	ID_HACR   p15, c1, 4, c1, 7
#define	ID_TTBR0   p15, c2, 0, c0, 0
#define	ID_TTBR1   p15, c2, 0, c0, 1
#define	ID_TTBCR   p15, c2, 0, c0, 2
#define	ID_HTCR   p15, c2, 4, c0, 2
#define	ID_VTCR   p15, c2, 4, c1, 2
#define	ID_DACR   p15, c3, 0, c0, 0
#define	ID_DFSR   p15, c5, 0, c0, 0
#define	ID_IFSR   p15, c5, 0, c0, 1
#define	ID_ADFSR   p15, c5, 0, c1, 0
#define	ID_AIFSR   p15, c5, 0, c1, 1
#define	ID_DFAR   p15, c6, 0, c0, 0
#define	ID_IFAR   p15, c6, 0, c0, 2
#define	ID_ICIALLUIS   p15, c7, 0, c1, 0
#define	ID_BPIALLUIS   p15, c7, 0, c1, 6
#define	ID_PAR   p15, c7, 0, c4, 0
#define	ID_ICIALLU   p15, c7, 0, c5, 0
#define	ID_ICIMVAU   p15, c7, 0, c5, 1
#define	ID_CP15ISB   p15, c7, 0, c5, 4
#define	ID_BPIALL   p15, c7, 0, c5, 6
#define	ID_BPIMVA   p15, c7, 0, c5, 7
#define	ID_DCIMVAC   p15, c7, 0, c6, 1
#define	ID_DCISW   p15, c7, 0, c6, 2
#define	ID_ATS1CPR   p15, c7, 0, c8, 0
#define	ID_ATS1CPW   p15, c7, 0, c8, 1
#define	ID_ATS1CUR   p15, c7, 0, c8, 2
#define	ID_ATS1CUW   p15, c7, 0, c8, 3
#define	ID_ATS12NSOPR   p15, c7, 0, c8, 4
#define	ID_ATS12NSOPW   p15, c7, 0, c8, 5
#define	ID_ATS12NSOUR   p15, c7, 0, c8, 6
#define	ID_ATS12NSOUW   p15, c7, 0, c8, 7
#define	ID_DCCMVAC   p15, c7, 0, c10, 1
#define	ID_DCCSW   p15, c7, 0, c10, 2
#define	ID_CP15DSB   p15, c7, 0, c10, 4
#define	ID_CP15DMB   p15, c7, 0, c10, 5
#define	ID_DCCMVAU   p15, c7, 0, c11, 1
#define	ID_DCCIMVAC   p15, c7, 0, c14, 1
#define	ID_DCCISW   p15, c7, 0, c14, 2
#define	ID_ATS1HR   p15, c7, 4, c8, 0
#define	ID_ATS1HW   p15, c7, 4, c8, 1
#define	ID_TLBIALL   p15, c8, 0, c7, 0
#define	ID_TLBIMVA   p15, c8, 0, c7, 1
#define	ID_TLBIASID   p15, c8, 0, c7, 2
#define	ID_TLBIMVAA   p15, c8, 0, c7, 3
#define	ID_VBAR   p15, c12, 0, c0, 0
#define	ID_MVBAR   p15, c12, 0, c0, 1
#define	ID_ISR   p15, c12, 0, c1, 0
#define	ID_HVBAR   p15, c12, 4, c0, 0
#define	ID_FCSEIDR   p15, c13, 0, c0, 0
#define	ID_CONTEXTIDR   p15, c13, 0, c0, 1
#define	CP_READ_ASM(reg, pn, n, opc1, m, opc2)   mrc pn, opc1, reg, n, m, opc2
#define	CP_WRITE_ASM(reg, pn, n, opc1, m, opc2)   mcr pn, opc1, reg, n, m, opc2
#define	CP_READ(reg, pn, n, opc1, m, opc2)
#define	CP_WRITE(reg, pn, n, opc1, m, opc2)
#define	READ_CP_ASM(dst, id)   CP_READ_ASM(dst,id)
#define	WRITE_CP_ASM(src, id)   CP_WRITE_ASM(src,id)
#define	READ_CP(dst, id)   CP_READ(dst,id)
#define	WRITE_CP(src, id)   CP_WRITE(src,id)
#define	DMB()   asm("dmb")
#define	READ_CPSR(reg)   asm("mrs %0, cpsr ":"=r"(reg))
#define	WRITE_CPSR(reg)   asm("msr cpsr_fc, %0"::"r"(reg))
#define	DSB()
#define	ISB()
#define	WRITE_TLBIASID(val)
#define	WRITE_TTBR0(val)

Macro Definition Documentation

ARM_MODE_ABORT

#define ARM_MODE_ABORT   (0x17)

ARM_MODE_FIQ

#define ARM_MODE_FIQ   (0x11)

ARM_MODE_HYP

#define ARM_MODE_HYP   (0x1A)

ARM_MODE_IRQ

#define ARM_MODE_IRQ   (0x12)

ARM_MODE_MON

#define ARM_MODE_MON   (0x16)

ARM_MODE_SVC

#define ARM_MODE_SVC   (0x13)

ARM_MODE_SYSTEM

#define ARM_MODE_SYSTEM   (0x1F)

ARM_MODE_UNDEF

#define ARM_MODE_UNDEF   (0x1B)

ARM_MODE_USER

#define ARM_MODE_USER   (0x10)

CP_READ

#define CP_READ	(		reg,
			pn,
			n,
			opc1,
			m,
			opc2
	)

Value:

asm("mrc " #pn ", " #opc1 ", %0, " #n ", " #m ", " #opc2    \
        : "=r"(reg));

CP_READ_ASM

#define CP_READ_ASM	(		reg,
			pn,
			n,
			opc1,
			m,
			opc2
	)		mrc pn, opc1, reg, n, m, opc2

CP_WRITE

#define CP_WRITE	(		reg,
			pn,
			n,
			opc1,
			m,
			opc2
	)

Value:

asm("mcr " #pn ", #" #opc1 ", %0, " #n ", " #m ", #" #opc2  \
        :: "r"(reg));

CP_WRITE_ASM

#define CP_WRITE_ASM	(		reg,
			pn,
			n,
			opc1,
			m,
			opc2
	)		mcr pn, opc1, reg, n, m, opc2

CPSR_A

#define CPSR_A   (1<<8)

CPSR_CARRY

#define CPSR_CARRY   (1<<29)

CPSR_E

#define CPSR_E   (1<<9)

CPSR_FIQ

#define CPSR_FIQ   (1<<6)

CPSR_IRQ

#define CPSR_IRQ   (1<<7)

CPSR_JAZELLE

#define CPSR_JAZELLE   (1<<24)

CPSR_NEGATIVE

#define CPSR_NEGATIVE   (1<<31)

CPSR_OVERFLOW

#define CPSR_OVERFLOW   (1<<28)

CPSR_THUMB

#define CPSR_THUMB   (1<<5)

CPSR_UNDERFLOW

#define CPSR_UNDERFLOW   (1<<27)

CPSR_ZERO

#define CPSR_ZERO   (1<<30)

DMB

#define DMB

(

)

asm("dmb")

DSB

#define DSB

(

)

Value:

asm volatile (                      \
        "dsb"                       \
        :                           \
        :                           \
        : "memory"                  \
    )

ID_ACTLR

#define ID_ACTLR   p15, c1, 0, c0, 1

ID_ADFSR

#define ID_ADFSR   p15, c5, 0, c1, 0

ID_AFR0

#define ID_AFR0   p15, c0, 0, c1, 3

ID_AIDR

#define ID_AIDR   p15, c0, 1, c0, 7

ID_AIFSR

#define ID_AIFSR   p15, c5, 0, c1, 1

ID_ATS12NSOPR

#define ID_ATS12NSOPR   p15, c7, 0, c8, 4

ID_ATS12NSOPW

#define ID_ATS12NSOPW   p15, c7, 0, c8, 5

ID_ATS12NSOUR

#define ID_ATS12NSOUR   p15, c7, 0, c8, 6

ID_ATS12NSOUW

#define ID_ATS12NSOUW   p15, c7, 0, c8, 7

ID_ATS1CPR

#define ID_ATS1CPR   p15, c7, 0, c8, 0

ID_ATS1CPW

#define ID_ATS1CPW   p15, c7, 0, c8, 1

ID_ATS1CUR

#define ID_ATS1CUR   p15, c7, 0, c8, 2

ID_ATS1CUW

#define ID_ATS1CUW   p15, c7, 0, c8, 3

ID_ATS1HR

#define ID_ATS1HR   p15, c7, 4, c8, 0

ID_ATS1HW

#define ID_ATS1HW   p15, c7, 4, c8, 1

ID_BPIALL

#define ID_BPIALL   p15, c7, 0, c5, 6

ID_BPIALLUIS

#define ID_BPIALLUIS   p15, c7, 0, c1, 6

ID_BPIMVA

#define ID_BPIMVA   p15, c7, 0, c5, 7

ID_CCSELR

#define ID_CCSELR   p15, c0, 2, c0, 0

ID_CCSIDR

#define ID_CCSIDR   p15, c0, 1, c0, 0

ID_CLIDR

#define ID_CLIDR   p15, c0, 1, c0, 1

ID_CONTEXTIDR

#define ID_CONTEXTIDR   p15, c13, 0, c0, 1

ID_CP15DMB

#define ID_CP15DMB   p15, c7, 0, c10, 5

ID_CP15DSB

#define ID_CP15DSB   p15, c7, 0, c10, 4

ID_CP15ISB

#define ID_CP15ISB   p15, c7, 0, c5, 4

ID_CPACR

#define ID_CPACR   p15, c1, 0, c0, 2

ID_CTR

#define ID_CTR   p15, c0, 0, c0, 1

ID_DACR

#define ID_DACR   p15, c3, 0, c0, 0

ID_DCCIMVAC

#define ID_DCCIMVAC   p15, c7, 0, c14, 1

ID_DCCISW

#define ID_DCCISW   p15, c7, 0, c14, 2

ID_DCCMVAC

#define ID_DCCMVAC   p15, c7, 0, c10, 1

ID_DCCMVAU

#define ID_DCCMVAU   p15, c7, 0, c11, 1

ID_DCCSW

#define ID_DCCSW   p15, c7, 0, c10, 2

ID_DCIMVAC

#define ID_DCIMVAC   p15, c7, 0, c6, 1

ID_DCISW

#define ID_DCISW   p15, c7, 0, c6, 2

ID_DFAR

#define ID_DFAR   p15, c6, 0, c0, 0

ID_DFR0

#define ID_DFR0   p15, c0, 0, c1, 2

ID_DFSR

#define ID_DFSR   p15, c5, 0, c0, 0

ID_FCSEIDR

#define ID_FCSEIDR   p15, c13, 0, c0, 0

ID_HACR

#define ID_HACR   p15, c1, 4, c1, 7

ID_HACTLR

#define ID_HACTLR   p15, c1, 4, c0, 1

ID_HCPTR

#define ID_HCPTR   p15, c1, 4, c1, 2

ID_HCR

#define ID_HCR   p15, c1, 4, c1, 0

ID_HDCR

#define ID_HDCR   p15, c1, 4, c1, 1

ID_HSCTLR

#define ID_HSCTLR   p15, c1, 4, c0, 0

ID_HSTR

#define ID_HSTR   p15, c1, 4, c1, 3

ID_HTCR

#define ID_HTCR   p15, c2, 4, c0, 2

ID_HVBAR

#define ID_HVBAR   p15, c12, 4, c0, 0

ID_ICIALLU

#define ID_ICIALLU   p15, c7, 0, c5, 0

ID_ICIALLUIS

#define ID_ICIALLUIS   p15, c7, 0, c1, 0

ID_ICIMVAU

#define ID_ICIMVAU   p15, c7, 0, c5, 1

ID_IFAR

#define ID_IFAR   p15, c6, 0, c0, 2

ID_IFSR

#define ID_IFSR   p15, c5, 0, c0, 1

ID_ISAR0

#define ID_ISAR0   p15, c0, 0, c2, 0

ID_ISAR1

#define ID_ISAR1   p15, c0, 0, c2, 1

ID_ISAR2

#define ID_ISAR2   p15, c0, 0, c2, 2

ID_ISAR3

#define ID_ISAR3   p15, c0, 0, c2, 3

ID_ISAR4

#define ID_ISAR4   p15, c0, 0, c2, 4

ID_ISAR5

#define ID_ISAR5   p15, c0, 0, c2, 5

ID_ISR

#define ID_ISR   p15, c12, 0, c1, 0

ID_MIDR

#define ID_MIDR   p15, c0, 0, c0, 0

ID_MMFR0

#define ID_MMFR0   p15, c0, 0, c1, 4

ID_MMFR1

#define ID_MMFR1   p15, c0, 0, c1, 5

ID_MMFR2

#define ID_MMFR2   p15, c0, 0, c1, 6

ID_MMFR3

#define ID_MMFR3   p15, c0, 0, c1, 7

ID_MPIDR

#define ID_MPIDR   p15, c0, 0, c0, 5

ID_MVBAR

#define ID_MVBAR   p15, c12, 0, c0, 1

ID_NSACR

#define ID_NSACR   p15, c1, 0, c1, 2

ID_PAR

#define ID_PAR   p15, c7, 0, c4, 0

ID_PFR0

#define ID_PFR0   p15, c0, 0, c1, 0

ID_PFR1

#define ID_PFR1   p15, c0, 0, c1, 1

ID_REVIDR

#define ID_REVIDR   p15, c0, 0, c0, 6

ID_SCR

#define ID_SCR   p15, c1, 0, c1, 0

ID_SCTLR

#define ID_SCTLR   p15, c1, 0, c0, 0

ID_SDER

#define ID_SDER   p15, c1, 0, c1, 1

ID_TCMTR

#define ID_TCMTR   p15, c0, 0, c0, 2

ID_TLBIALL

#define ID_TLBIALL   p15, c8, 0, c7, 0

ID_TLBIASID

#define ID_TLBIASID   p15, c8, 0, c7, 2

ID_TLBIMVA

#define ID_TLBIMVA   p15, c8, 0, c7, 1

ID_TLBIMVAA

#define ID_TLBIMVAA   p15, c8, 0, c7, 3

ID_TLBTR

#define ID_TLBTR   p15, c0, 0, c0, 3

ID_TTBCR

#define ID_TTBCR   p15, c2, 0, c0, 2

ID_TTBR0

#define ID_TTBR0   p15, c2, 0, c0, 0

ID_TTBR1

#define ID_TTBR1   p15, c2, 0, c0, 1

ID_VBAR

#define ID_VBAR   p15, c12, 0, c0, 0

ID_VMPIDR

#define ID_VMPIDR   p15, c0, 4, c0, 5

ID_VPIDR

#define ID_VPIDR   p15, c0, 4, c0, 0

ID_VTCR

#define ID_VTCR   p15, c2, 4, c1, 2

ISB

#define ISB

(

)

Value:

asm volatile (                      \
        "isb"                       \
        :                           \
        :                           \
        : "memory"                  \
    )

READ_CP

#define READ_CP	(		dst,
			id
	)		CP_READ(dst,id)

READ_CP_ASM

#define READ_CP_ASM	(		dst,
			id
	)		CP_READ_ASM(dst,id)

READ_CPSR

#define READ_CPSR

(

reg

)

asm("mrs %0, cpsr ":"=r"(reg))

SCTLR_AFE

#define SCTLR_AFE   (1<<29)

SCTLR_ALIGH

#define SCTLR_ALIGH   (1<<1)

SCTLR_BRANCH_PRED

#define SCTLR_BRANCH_PRED   (1<<11)

SCTLR_CP15BEN

#define SCTLR_CP15BEN   (1<<5)

SCTLR_DCACHE

#define SCTLR_DCACHE   (1<<2)

SCTLR_EE

#define SCTLR_EE   (1<<25)

SCTLR_ENDIAN

#define SCTLR_ENDIAN   (1<<7)

SCTLR_FASTINT

#define SCTLR_FASTINT   (1<<21)

SCTLR_HWACCESS

#define SCTLR_HWACCESS   (1<<17)

SCTLR_ICACHE

#define SCTLR_ICACHE   (1<<12)

SCTLR_MMU

#define SCTLR_MMU   (1)

SCTLR_NMFI

#define SCTLR_NMFI   (1<<27)

SCTLR_ROUNDROBIN

#define SCTLR_ROUNDROBIN   (1<<14)

SCTLR_SWP

#define SCTLR_SWP   (1<<10)

SCTLR_THUMBEXC

#define SCTLR_THUMBEXC   (1<<30)

SCTLR_TRE

#define SCTLR_TRE   (1<<28)

SCTLR_U

#define SCTLR_U   (1<<22)

SCTLR_UWXN

#define SCTLR_UWXN   (1<<20)

SCTLR_VE

#define SCTLR_VE   (1<<24)

SCTLR_VECTOR

#define SCTLR_VECTOR   (1<<13)

SCTLR_WXN

#define SCTLR_WXN   (1<<19)

WRITE_CP

#define WRITE_CP	(		src,
			id
	)		CP_WRITE(src,id)

WRITE_CP_ASM

#define WRITE_CP_ASM	(		src,
			id
	)		CP_WRITE_ASM(src,id)

WRITE_CPSR

#define WRITE_CPSR

(

reg

)

asm("msr cpsr_fc, %0"::"r"(reg))

WRITE_TLBIASID

#define WRITE_TLBIASID

(

val

)

Value:

asm volatile (                      \
        "mcr p15, 0, %0, c8, c7, 2" \
        :                           \
        : "r" (val)                 \
        : "memory"                  \
    )

WRITE_TTBR0

#define WRITE_TTBR0

(

val

)

Value:

asm volatile (                      \
        "mcr p15, 0, %0, c2, c0, 0" \
        :                           \
        : "r" (val)                 \
        : "memory"                  \
    )