Pip
Architecture-dependent parts of Pip: MAL, IAL and boot
coproc.h
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2 /* © Université de Lille, The Pip Development Team (2015-2021) */
3 /* */
4 /* This software is a computer program whose purpose is to run a minimal, */
5 /* hypervisor relying on proven properties such as memory isolation. */
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32 /*******************************************************************************/
33 
34 #ifndef COPROC_H_
35 #define COPROC_H_
36 
37 /* Definitions for ARMv7-A/R */
38 
39 #define CPSR_NEGATIVE (1<<31)
40 #define CPSR_ZERO (1<<30)
41 #define CPSR_CARRY (1<<29)
42 #define CPSR_OVERFLOW (1<<28)
43 #define CPSR_UNDERFLOW (1<<27)
44 #define CPSR_JAZELLE (1<<24)
45 #define CPSR_E (1<<9)
46 #define CPSR_A (1<<8)
47 #define CPSR_IRQ (1<<7)
48 #define CPSR_FIQ (1<<6)
49 #define CPSR_THUMB (1<<5)
50 
51 #define ARM_MODE_USER (0x10)
52 #define ARM_MODE_FIQ (0x11)
53 #define ARM_MODE_IRQ (0x12)
54 #define ARM_MODE_SVC (0x13)
55 #define ARM_MODE_MON (0x16)
56 #define ARM_MODE_ABORT (0x17)
57 #define ARM_MODE_HYP (0x1A)
58 #define ARM_MODE_UNDEF (0x1B)
59 #define ARM_MODE_SYSTEM (0x1F)
60 
61 /* B4.1.130: SCTLR */
62 #define SCTLR_MMU (1)
63 #define SCTLR_ALIGH (1<<1)
64 #define SCTLR_DCACHE (1<<2)
65 #define SCTLR_CP15BEN (1<<5)
66 #define SCTLR_ENDIAN (1<<7)
67 #define SCTLR_SWP (1<<10)
68 #define SCTLR_BRANCH_PRED (1<<11)
69 #define SCTLR_ICACHE (1<<12)
70 #define SCTLR_VECTOR (1<<13)
71 #define SCTLR_ROUNDROBIN (1<<14)
72 #define SCTLR_HWACCESS (1<<17)
73 #define SCTLR_WXN (1<<19)
74 #define SCTLR_UWXN (1<<20)
75 #define SCTLR_FASTINT (1<<21)
76 #define SCTLR_U (1<<22)
77 #define SCTLR_VE (1<<24)
78 #define SCTLR_EE (1<<25)
79 #define SCTLR_NMFI (1<<27)
80 #define SCTLR_TRE (1<<28)
81 #define SCTLR_AFE (1<<29)
82 #define SCTLR_THUMBEXC (1<<30)
83 
84 /* B3.17.1: CP15 register summary by coprocessor register number */
85 #define ID_MIDR p15, c0, 0, c0, 0
86 #define ID_CTR p15, c0, 0, c0, 1
87 #define ID_TCMTR p15, c0, 0, c0, 2
88 #define ID_TLBTR p15, c0, 0, c0, 3
89 #define ID_MPIDR p15, c0, 0, c0, 5
90 #define ID_REVIDR p15, c0, 0, c0, 6
91 
92 #define ID_PFR0 p15, c0, 0, c1, 0
93 #define ID_PFR1 p15, c0, 0, c1, 1
94 #define ID_DFR0 p15, c0, 0, c1, 2
95 #define ID_AFR0 p15, c0, 0, c1, 3
96 #define ID_MMFR0 p15, c0, 0, c1, 4
97 #define ID_MMFR1 p15, c0, 0, c1, 5
98 #define ID_MMFR2 p15, c0, 0, c1, 6
99 #define ID_MMFR3 p15, c0, 0, c1, 7
100 
101 #define ID_ISAR0 p15, c0, 0, c2, 0
102 #define ID_ISAR1 p15, c0, 0, c2, 1
103 #define ID_ISAR2 p15, c0, 0, c2, 2
104 #define ID_ISAR3 p15, c0, 0, c2, 3
105 #define ID_ISAR4 p15, c0, 0, c2, 4
106 #define ID_ISAR5 p15, c0, 0, c2, 5
107 
108 #define ID_CCSIDR p15, c0, 1, c0, 0
109 #define ID_CLIDR p15, c0, 1, c0, 1
110 #define ID_AIDR p15, c0, 1, c0, 7
111 
112 #define ID_CCSELR p15, c0, 2, c0, 0
113 #define ID_VPIDR p15, c0, 4, c0, 0
114 #define ID_VMPIDR p15, c0, 4, c0, 5
115 
116 #define ID_SCTLR p15, c1, 0, c0, 0
117 #define ID_ACTLR p15, c1, 0, c0, 1
118 #define ID_CPACR p15, c1, 0, c0, 2
119 
120 #define ID_SCR p15, c1, 0, c1, 0
121 #define ID_SDER p15, c1, 0, c1, 1
122 #define ID_NSACR p15, c1, 0, c1, 2
123 
124 #define ID_HSCTLR p15, c1, 4, c0, 0
125 #define ID_HACTLR p15, c1, 4, c0, 1
126 
127 #define ID_HCR p15, c1, 4, c1, 0
128 #define ID_HDCR p15, c1, 4, c1, 1
129 #define ID_HCPTR p15, c1, 4, c1, 2
130 #define ID_HSTR p15, c1, 4, c1, 3
131 #define ID_HACR p15, c1, 4, c1, 7
132 
133 #define ID_TTBR0 p15, c2, 0, c0, 0
134 #define ID_TTBR1 p15, c2, 0, c0, 1
135 #define ID_TTBCR p15, c2, 0, c0, 2
136 #define ID_HTCR p15, c2, 4, c0, 2
137 #define ID_VTCR p15, c2, 4, c1, 2
138 
139 #define ID_DACR p15, c3, 0, c0, 0
140 
141 #define ID_DFSR p15, c5, 0, c0, 0
142 #define ID_IFSR p15, c5, 0, c0, 1
143 #define ID_ADFSR p15, c5, 0, c1, 0
144 #define ID_AIFSR p15, c5, 0, c1, 1
145 #define ID_DFAR p15, c6, 0, c0, 0
146 #define ID_IFAR p15, c6, 0, c0, 2
147 
148 #define ID_ICIALLUIS p15, c7, 0, c1, 0
149 #define ID_BPIALLUIS p15, c7, 0, c1, 6
150 #define ID_PAR p15, c7, 0, c4, 0
151 #define ID_ICIALLU p15, c7, 0, c5, 0
152 #define ID_ICIMVAU p15, c7, 0, c5, 1
153 #define ID_CP15ISB p15, c7, 0, c5, 4
154 #define ID_BPIALL p15, c7, 0, c5, 6
155 #define ID_BPIMVA p15, c7, 0, c5, 7
156 #define ID_DCIMVAC p15, c7, 0, c6, 1
157 #define ID_DCISW p15, c7, 0, c6, 2
158 #define ID_ATS1CPR p15, c7, 0, c8, 0
159 #define ID_ATS1CPW p15, c7, 0, c8, 1
160 #define ID_ATS1CUR p15, c7, 0, c8, 2
161 #define ID_ATS1CUW p15, c7, 0, c8, 3
162 #define ID_ATS12NSOPR p15, c7, 0, c8, 4
163 #define ID_ATS12NSOPW p15, c7, 0, c8, 5
164 #define ID_ATS12NSOUR p15, c7, 0, c8, 6
165 #define ID_ATS12NSOUW p15, c7, 0, c8, 7
166 #define ID_DCCMVAC p15, c7, 0, c10, 1
167 #define ID_DCCSW p15, c7, 0, c10, 2
168 #define ID_CP15DSB p15, c7, 0, c10, 4
169 #define ID_CP15DMB p15, c7, 0, c10, 5
170 #define ID_DCCMVAU p15, c7, 0, c11, 1
171 #define ID_DCCIMVAC p15, c7, 0, c14, 1
172 #define ID_DCCISW p15, c7, 0, c14, 2
173 #define ID_ATS1HR p15, c7, 4, c8, 0
174 #define ID_ATS1HW p15, c7, 4, c8, 1
175 
176 #define ID_TLBIALL p15, c8, 0, c7, 0
177 #define ID_TLBIMVA p15, c8, 0, c7, 1
178 #define ID_TLBIASID p15, c8, 0, c7, 2
179 #define ID_TLBIMVAA p15, c8, 0, c7, 3
180 
181 #define ID_VBAR p15, c12, 0, c0, 0
182 #define ID_MVBAR p15, c12, 0, c0, 1
183 #define ID_ISR p15, c12, 0, c1, 0
184 #define ID_HVBAR p15, c12, 4, c0, 0
185 
186 #define ID_FCSEIDR p15, c13, 0, c0, 0
187 #define ID_CONTEXTIDR p15, c13, 0, c0, 1
188 
189 #define CP_READ_ASM(reg, pn, n,opc1,m,opc2) \
190  mrc pn, opc1, reg, n, m, opc2
191 #define CP_WRITE_ASM(reg, pn, n,opc1,m,opc2) \
192  mcr pn, opc1, reg, n, m, opc2
193 
194 #define CP_READ(reg, pn, n,opc1,m,opc2) \
195  asm("mrc " #pn ", " #opc1 ", %0, " #n ", " #m ", " #opc2 \
196  : "=r"(reg));
197 #define CP_WRITE(reg, pn, n,opc1,m,opc2) \
198  asm("mcr " #pn ", #" #opc1 ", %0, " #n ", " #m ", #" #opc2 \
199  :: "r"(reg));
200 
201 #define READ_CP_ASM(dst,id) CP_READ_ASM(dst,id)
202 #define WRITE_CP_ASM(src,id) CP_WRITE_ASM(src,id)
203 #define READ_CP(dst,id) CP_READ(dst,id)
204 #define WRITE_CP(src,id) CP_WRITE(src,id)
205 
206 #define DMB() asm("dmb")
207 
208 #define READ_CPSR(reg) asm("mrs %0, cpsr ":"=r"(reg))
209 #define WRITE_CPSR(reg) asm("msr cpsr_fc, %0"::"r"(reg))
210 
211 /* ============================================= */
212 
213 #define DSB() \
214  asm volatile ( \
215  "dsb" \
216  : \
217  : \
218  : "memory" \
219  )
220 
221 #define ISB() \
222  asm volatile ( \
223  "isb" \
224  : \
225  : \
226  : "memory" \
227  )
228 
229 #define WRITE_TLBIASID(val) \
230  asm volatile ( \
231  "mcr p15, 0, %0, c8, c7, 2" \
232  : \
233  : "r" (val) \
234  : "memory" \
235  )
236 
237 #define WRITE_TTBR0(val) \
238  asm volatile ( \
239  "mcr p15, 0, %0, c2, c0, 0" \
240  : \
241  : "r" (val) \
242  : "memory" \
243  )
244 
245 #endif
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